Some projects involve files that are scattared amoung multiple directories. If the files associated with these directories are regular design files then simply adding the design files to the project is sufficient for making sure they are included in the project. When these files are ‘include’ files, however, you need to add the directory as an additiona “include” directory. This document summarizes how to add an additional include directory.
Method 1 - TCL Command
You can add an include directory by executing the following command (replace
set_property include_dirs <path> [current_fileset]
Method 2 - GUI
You can add a directory by completing the following GUI steps.
Select Project Manager->Settings to open project settings dialog box
Select the “…” icon next to the ‘Verilog Options’ under the ‘Language Options’ on the right side pane of the project settings dialog box
Press ‘+’ on the “Verilog Include Files Search Paths” section of the Verilog Options dialog box
Select the directory for the include path.